Integrated circuit chips often are mounted in chip carriers of dielectric material from which conductors of the integrated circuit extend. A chip carrier socket assembly commonly is provided with an insulating housing and a cover. The housing has a receptacle for receiving the chip carrier and the cover is positioned about the chip carrier when the chip carrier is positioned in the receptacle. The housing mounts a plurality of terminals adjacent the receptacle for contacting the conductors or leads extending from the chip carrier. The housing may be of the type for mounting to a printed circuit board, with the terminals engaging circuit traces on the board, or the housing may be otherwise configured for interconnecting the terminals with a complementary electrical component. Examples of such chip carrier sockets as described above are shown in U.S. Pat. Nos. 4,872,845 to Korsunsky et dated Oct. 10, 1989; 4,886,470 to Billman et al, dated Dec. 12, 1989; and 4,968,259 to Korsunsky et al, dated Nov. 6, 1990.
In chip carrier socket assemblies as described above, some form of latching means commonly is provided between the housing and the cover to retain the cover on the housing with the chip carrier secured therebetween in the receptacle of the housing and with the housing terminals engaging the conductors extending from the chip carrier. For instance, the terminals on the housing may have resilient latch arms for interengaging with the cover, or the housing itself may have a resilient latch arm for interengaging with the cover, as shown in one or more of the above-referenced U.S. patents. Due to the high density, miniaturized nature of integrated circuit chips and the miniaturized configuration the chip carrier and socket components, it is difficult to achieve sufficient resiliency in the design of the latch means. In addition, the latch means often are exposed exteriorly of the socket housing and easily can become unintentionally unlatched by engagement with a foreign object.
This invention is directed to solving these problems by providing a latch means in a chip carrier socket assembly which has improved resiliency and which is concealed totally within the socket assembly, yet which is readily disengaged to open the assembly.